Research on Data Acquisition Technology of Digital Medical Equipment Ultrasonic Flaw Detector

Ultrasound has always been an indispensable technology in the field of medical equipment, with strong penetrating power and high detection sensitivity. However, his current application will no longer be limited to medical care, such as in aerospace, metallurgical and other manufacturing industries. Today, ultrasonic flaw detectors that use ultrasonic non-destructive testing technology are analog and digital. With the development of computer technology, microelectronics technology and digital signal processing technology, traditional analog ultrasonic flaw detectors are gradually being advanced. Replaced by a digital ultrasonic flaw detector.

The echo signal of the ultrasonic wave is a high frequency signal, and its center frequency is up to 20 MHz. The frequency of the echo signal in the commonly used ultrasonic probe is generally 2.5 to 10 MHz. To digitize such a high frequency signal, the system is The analog-to-digital conversion circuit places high demands on it. According to the Shannon sampling theorem and the Nyquist sampling criterion, in an ideal data acquisition system, in order to reproduce the input signal without distortion, the sampling frequency is at least twice the highest frequency of the input signal. In actual use, in order to ensure the accuracy of data acquisition, the number of samples in each input signal period should be increased, generally 7 to 10 times per cycle. Some systems have higher requirements for the frequency of the sampled signal. The existing A/D conversion circuit schemes have many shortcomings in reliability, power consumption, sampling speed and accuracy, which cannot meet the needs of some actual situations, and the development of large-scale integrated circuit technology is high-speed, high-precision design. High reliability, low power ultrasound signal acquisition solutions offer the possibility. In this paper, an ultrasonic acquisition module with a sampling rate of 100 MHz is designed, and the sampled data is compressed by the FPGA to buffer the data.

Digital ultrasonic flaw detector structure block diagram shown in Figure 1.

The digital ultrasonic flaw detector generally includes an ultrasonic transmitting unit, an ultrasonic receiving unit, a signal conditioning unit (including analog signal processing steps such as amplification, detection, filtering, etc.), an analog-to-digital (A/D) conversion unit, a data buffer unit, a data processing unit, and a waveform. Display unit and system control and input/output unit (including communication, keyboard operation, alarm, etc.). This paper mainly discusses the key technologies and implementation methods of high-speed acquisition in digital ultrasonic flaw detectors, involving A/D conversion unit and data buffer unit.

2.1 Block diagram of the data acquisition module

Figure 2 shows the hardware block diagram of the data acquisition module of this paper, which consists of high-speed A / D data converter, FPGA, clock circuit, reset circuit and power circuit. Among them, the A/D data converter is responsible for the acquisition and conversion of the analog signal; the FPGA is responsible for acquisition control, data compression and data buffering. The following describes the A/D data converter and FPGA.

2.2 Introduction to AD9446

The AD9446 is a 16 b ADC with a sampling rate of up to 100 MSPS with integrated high performance sample and hold and a reference voltage source. Like most high speed, large dynamic range ADC chips, the AD9446 is also a differential input that provides excellent rejection of even and common mode signals. The AD9446 can operate in CMOS mode and low voltage differential signaling (LVD-S) mode, with mode setting via the output logic control pin. In addition, the digital output of the AD9446 is also optional. Can be direct binary source or twos complement. In the PCB design of the actual circuit, since the AD9446 is a noise-sensitive analog device, the following aspects should be implemented in the specific PCB design: A/D analog power supply separately, analog ground and digital ground single point ground, differential The input lines are of equal length and use an accurate reference voltage source.

2.3 FPGA implementation of acquisition control, data compression and data buffering

FPGA mainly realizes the functions of data acquisition control, data compression and data buffering of the entire module. The FPGA uses Xilinx's Spartan3E series (XC3S500E). This FPGA chip is powerful and has a wealth of I/O resources to meet the needs of many practical situations. The following describes the design of data acquisition control, data compression and data buffer FIFO.

2.3.1 Data Acquisition Control

The control timing of the AD9446 chip is different from the traditional low-speed A/D. It relies entirely on the clock to control its sampling, conversion, and data output. The AD9446 typically begins sampling conversion on the rising edge of the first clock of CLK and begins to output data after a delay of tpd. The data appears on the D15 to D0 ports only when the 13th clock arrives. Figure 3 is a timing diagram of the AD9446 operating in CMOS mode.

The Digital Clock Management Unit (DCM) is a dedicated module for managing and controlling the clock inside the FPGA. It can perform functions such as frequency division, multiplication, debounce, and phase shift. The clock input signal of the AD9446 can be easily controlled by the DCM of the FPGA. In the actual circuit, it should be noted that the clock signal of the DCM multiplier output is matched with the clock input signal of the AD9446.

The VHDL language description of the clock output after calling DCM is given below:

2.3.2 Data Compression

Data compression processing is one of the important steps in pre-processing the high-frequency sampling of RF signals. It is necessary to compress the sampling data online while maintaining the basic characteristics of the ultrasonic echo signals, and requires the compressed data and the original sampling signal package. The network is consistent. For this reason, in each compression process, only the maximum value obtained by sampling is taken, and other sample values ​​are discarded. The FPGA sends the calculated compression ratio of the sampled data, the probe leading edge delay count value and other data to the corresponding latch, then issues a timing reset command and transmits, starts the probe delay counting, and starts the A/D sampling after the delay. At the same time, the compression ratio counter starts counting. Under the control of the clock signal, each time the sample is sampled, the compression ratio counter is decremented by 1, and the current sample value is compared with the previous sampled value. If it is greater than, the value is saved, otherwise it is discarded until the compression ratio is counted to zero. After that, get a valid sampled data. At the same time, the compression ratio counter is automatically reset and restarts counting. The workflow is shown in Figure 4.

2.3.3 Data buffering

In order to solve the problem of rate mismatch between front-end data acquisition and back-end data transmission, a data buffer FIFO is set inside the FPGA, the size is 8K & TImes; 16 b, the compressed data is directly stored in the FIFO, and the microprocessor is FIFO. The reading of the data is completed by the interrupt method. The data buffer FIFO is instantiated by the core generator, and only a small amount of read/write control logic is required to make the FIFO work normally, and the size of the FIFO can be flexibly set within the range of RAM bits provided by the FPGA. The VHDL language description of the instantiated FIFO is given below:

The data stored in the FIFO is facilitated by the microprocessor to read, clear, etc. through these logical control ports.

The data acquisition module based on AD9446 is designed to realize data acquisition control, data compression and data buffering functions. It simplifies the hardware circuit, improves the reliability and stability of the module, and facilitates the function upgrade of the module. At the same time, the high-speed high-precision analog-to-digital converter is used to meet the requirements of digital ultrasonic flaw detection system for data acquisition accuracy. In addition, FP-GA preprocesses the data, which facilitates the call and post processing of the data by the microprocessor.

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2.0mm Female Pin Header

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Overview

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